1. Field of the Invention
The present invention generally relates to the fields of semiconductor fabrication and shallow trench isolation techniques. More particularly, the present invention provides a method of using a silicate alloy trench fill process to reduce stress in a shallow trench isolation region of a MOSFET device.
2. Brief Description of the Related Art
Shallow trench isolation (STI) technology represents a superior application of device-level processing primarily for devices at or below 0.25 microns. Shallow trench isolation provides for better packing density. However, as devices become smaller and more densely packed, problems associated with stress due to trench processing, particularly thermal cycling, occur. Smaller device geometries require higher aspect ratios in shallow trenches and dielectric films deposited into these high aspect ratio trenches are more prone to containing gaps and voids. Additionally, these dielectric films must exhibit low shrinkage during subsequent heating steps to eliminate the formation of gaps and voids in the dielectric fill. Such defects contribute to performance unreliability of the device.
Compressive stress in silicon, through the piezoresistive effect is responsible for the degradation of electron mobility and creates a reduced-mobility area near the trench edge. If it is severe enough, anisotropic compressive stress generated during shallow trench formation causes crystalline defects or dislocations in the silicon substrate resulting in high leakage currents. With extra annealing steps, stress can be reduced and dislocations minimized. The anneal conditions limit device design and may not be preferred (FIG. 1). However, in shallow trench isolation structures in highly integrated semiconductor devices, the profile of the edge of the shallow trench determines the electrical characteristics of the device.
It has been suggested that a polysilicon dielectric fill be deposited in the shallow trench and oxidized therein. A narrow width trench is completely filled during the oxidation of the polysilicon within the trench because of volumetric expansion. However, stress is applied at the active region of the sidewall of the trench. Also, due to step coverage limitations of the polysilicon within the trench, it is difficult to effectively prevent a collapse of the upper edge of the trench.
A Metal Oxide Silicon Field Effect Transistor (MOSFET) uses an oxide film as an insulator. Typically, an n-MOSFET or NMOS structure is comprised of paired n-type source and drain regions implanted in the surface of a silicon substrate, of a gate oxide film formed on the silicon substrate between the source and the drain regions and of a gate electrode formed on the surface of the gate oxide film (FIG. 2). In an NMOS device, the PWell may be doped with boron. A channel region between the source region and the drain region is formed. The channel length, i.e., the distance between the source and the drain, is shorter than the gate length.
For an NMOS transistor to operate, a threshold voltage must be applied across the gate and the source electrodes. The amount of voltage applied at the gate necessary to reach this threshold is dependent upon such factors as the gate material, the gate insulation material, the gate insulation thickness, the channel doping, the impurities at the silicon-insulator interface, and the source-to-substrate voltage between the source and the substrate.
To increase the speed of MOSFET devices in general, structures are scaled down to smaller sizes. This means that the gate length is reduced with the concomitant reduction in channel length. Such scaling down can result in the loss of gate electrode control or voltage threshold roll-off. As the channel length of a transistor decreases, the threshold voltage also decreases causing an inverse narrow width effect.
When implementing a trench isolation structure, a strong electric field forms locally in a channel area proximate to the corner of the trench. Thus inversion can easily occur even at low voltages; the current that flows between the source and the drain thus increases. Stress of the active area of a device generated during STI fabrication only enhances the already increased voltage threshold roll-off resulting from the scaling down of MOSFETS and thereby degrades the electrical performance. Additionally, stress-induced dislocations at the sidewall can degrade yield of integrated circuit products. Solubility of dopants in the dielectric may be dependant on the fill material used, as thermal cycles during device fabrication occur.
Furthermore, with the thermal cycles necessary for device processing, together with the down-scaling of the gate and trench geometries, dopant diffusion, specifically boron in a n NMOS device, through the substrate to the sidewalls and/or through the gate structure and gate dielectric can cause damage to the device. This degrades the control over the threshold voltage of the narrow width devices. Hence, any b or on penetration into the channel region or segregation to the sidewalls causes loss of control over the threshold voltage of the device and hinders performance of the device.
The shallow trench isolation formation process induces compressive stress in the active area of a device and tensile stress at the shallow trench edges, particularly for narrow devices. It is essential to minimize stress during STI thermal cycling in order to maintain the integrity of the dielectric fill material along the trench edges and sidewalls and thereby to protect the active areas of MOSFET devices. The ability of the dielectric fill material to match the expansion/contraction properties of the silicon substrate in the device would significantly reduce such stress and thereby enhance electrical performance of the MOSFET device.
The prior art is deficient in the lack of an effective method of reducing stress in shallow trench isolation devices. The present invention fulfills this long-standing need and desire in the art.
In one embodiment, the present invention provides a method of reducing stress in a shallow trench isolation region of a MOSFET device comprising the step of forming a dielectric in the shallow trench isolation region wherein the thermal expansion coefficient of the dielectric approximates the thermal expansion coefficient of silicon in the substrate thereby reducing stress in the shallow trench isolation region.
In another embodiment, the present invention provides a method of reducing stress in a shallow trench isolation region of a MOSFET device comprising the steps of adding an aluminum trioxide precursor during deposition of silicon dioxide in a shallow trench isolation trench fill process in the device; and depositing an aluminosilicate alloy in the shallow trench such that a dielectric is formed in the shallow trench isolation region wherein the thermal expansion coefficient of the dielectric approximates the thermal expansion coefficient of silicon in the substrate, thereby reducing stress in the shallow trench isolation region.
In yet another embodiment, the present invention provides a method of forming a dielectric-filled, shallow trench isolation region for a MOSFET device, comprising the steps of forming a pad oxide film on a semiconductor substrate; forming a pad nitride film on the pad oxide film; forming a shallow trench in a field region of the semiconductor substrate through the pad nitride film and the pad oxide film; forming a liner oxide film at the inner walls of the shallow trench by oxidizing the semiconductor substrate; filling the shallow trench with a n aluminosilicate dielectric alloy; and planarizing the surface of the aluminosilicate dielectric alloy thereby forming a shallow trench isolation region.
Other and further aspects, features, and advantages of the present invention will be apparent from the following description of the invention.